Exposure to the Engineering process and methodologies, exposure to the complete lifecycle of ASIC Flow is essential.
Interface with the engineering team to gather requirements. Improves process and tools methodologies (as needed).
Creates requirement documents/SOW for the development team communicates effectively with the stakeholders.
Ability to prioritize, plan, coordinate and deliver on multiple tasks/projects simultaneously.
Ability to adjust and set priorities to meet deadlines.
Proficient in hands on SOC Design methodologies. Understanding of clocks in the design, Identification of clock domain crossing issues / missing synchronizers and ability resolve it.
Ability to generate correct constraints from spec. Have to drive to collate and arrive at constraints for sub-modules in discussion/consultation with sub-system owners.
Ability to understand review and apply appropriate waivers, exceptions. Should have good expertise in Full Chip FV, RTL – RTL FV, RTL – Netlist FV, Conformal ECO, and Non-EQ debug.
Education: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics